As Tesler’s Law says, a system exhibits a certain amount of complexity that cannot be reduced - it can only be shifted around. With Modular Design we move global complexity to modules, but with too fine-grained modules, the effect is negated, because small modules hide too little.
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Intel's 1986 ICCD paper Performance Optimizations of the 80386 reveals how tightly this was optimized. The entire address translation pipeline -- effective address calculation, segment relocation, and TLB lookup -- completes in 1.5 clock cycles: